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Self-aligned top-gate InGaZnO thin film transistors using SiO2/Al2O3 stack gate dielectric

Identifieur interne : 000563 ( Main/Repository ); précédent : 000562; suivant : 000564

Self-aligned top-gate InGaZnO thin film transistors using SiO2/Al2O3 stack gate dielectric

Auteurs : RBID : Pascal:14-0082273

Descripteurs français

Pascal (Inist)
- Electrode commande, Transistor couche mince, Oxyde d'indium, Oxyde de gallium, Oxyde de zinc, Couche mince, Interface, Couche active, Porte logique, Effet champ électrique, Seuil tension, Loi échelle, InGaZnO, Al2O3, 8530T, 8530P.

English descriptors

KwdEn :
- Active layer, Electric field effect, Gallium oxide, Gates, Indium oxide, Interface, Logic gate, Scaling law, Thin film, Thin film transistor, Voltage threshold, Zinc oxide.

Abstract

Self-aligned top-gate amorphous indium-gallium-zinc oxide (a-IGZO) thin film transistors (TFTs) utilizing SiO₂/ Al₂O₃ stack thin films as gate dielectric are developed in this paper. Due to high quality of the high-k Al₂O₃ and good interface between active layer and gate dielectric, the resulting a-IGZO TFT exhibits good electrical performance including field-effect mobility of 9 cm²/Vs, threshold voltage of 2.2 V, subthreshold swing of 0.2 V/decade, and on/off current ratio of 1 × 10⁷. With scaling down of the channel length, good characteristics are also obtained with a small shift of the threshold voltage and no degradation of subthreshold swing.

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Pascal:14-0082273

Le document en format XML

<record><TEI><teiHeader><fileDesc><titleStmt><title xml:lang="en" level="a">Self-aligned top-gate InGaZnO thin film transistors using SiO<sub>2</sub>
/Al<sub>2</sub>
O<sub>3</sub>
 stack gate dielectric</title>
<author><name>RONGSHENG CHEN</name>
<affiliation wicri:level="1"><inist:fA14 i1="01"><s1>Center for Display Research, Department of Electronic and Computer Engineering, Hong Kong University of Science and Technology, Clear Water Bay</s1>
<s2>Kowloon</s2>
<s3>HKG</s3>
<sZ>1 aut.</sZ>
<sZ>2 aut.</sZ>
<sZ>3 aut.</sZ>
<sZ>4 aut.</sZ>
<sZ>5 aut.</sZ>
</inist:fA14>
<country>Hong Kong</country>
<wicri:noRegion>Kowloon</wicri:noRegion>
</affiliation>
</author>
<author><name>WEI ZHOU</name>
<affiliation wicri:level="1"><inist:fA14 i1="01"><s1>Center for Display Research, Department of Electronic and Computer Engineering, Hong Kong University of Science and Technology, Clear Water Bay</s1>
<s2>Kowloon</s2>
<s3>HKG</s3>
<sZ>1 aut.</sZ>
<sZ>2 aut.</sZ>
<sZ>3 aut.</sZ>
<sZ>4 aut.</sZ>
<sZ>5 aut.</sZ>
</inist:fA14>
<country>Hong Kong</country>
<wicri:noRegion>Kowloon</wicri:noRegion>
</affiliation>
</author>
<author><name>MENG ZHANG</name>
<affiliation wicri:level="1"><inist:fA14 i1="01"><s1>Center for Display Research, Department of Electronic and Computer Engineering, Hong Kong University of Science and Technology, Clear Water Bay</s1>
<s2>Kowloon</s2>
<s3>HKG</s3>
<sZ>1 aut.</sZ>
<sZ>2 aut.</sZ>
<sZ>3 aut.</sZ>
<sZ>4 aut.</sZ>
<sZ>5 aut.</sZ>
</inist:fA14>
<country>Hong Kong</country>
<wicri:noRegion>Kowloon</wicri:noRegion>
</affiliation>
</author>
<author><name>MAN WONG</name>
<affiliation wicri:level="1"><inist:fA14 i1="01"><s1>Center for Display Research, Department of Electronic and Computer Engineering, Hong Kong University of Science and Technology, Clear Water Bay</s1>
<s2>Kowloon</s2>
<s3>HKG</s3>
<sZ>1 aut.</sZ>
<sZ>2 aut.</sZ>
<sZ>3 aut.</sZ>
<sZ>4 aut.</sZ>
<sZ>5 aut.</sZ>
</inist:fA14>
<country>Hong Kong</country>
<wicri:noRegion>Kowloon</wicri:noRegion>
</affiliation>
</author>
<author><name>HOI SING KWOK</name>
<affiliation wicri:level="1"><inist:fA14 i1="01"><s1>Center for Display Research, Department of Electronic and Computer Engineering, Hong Kong University of Science and Technology, Clear Water Bay</s1>
<s2>Kowloon</s2>
<s3>HKG</s3>
<sZ>1 aut.</sZ>
<sZ>2 aut.</sZ>
<sZ>3 aut.</sZ>
<sZ>4 aut.</sZ>
<sZ>5 aut.</sZ>
</inist:fA14>
<country>Hong Kong</country>
<wicri:noRegion>Kowloon</wicri:noRegion>
</affiliation>
</author>
</titleStmt>
<publicationStmt><idno type="inist">14-0082273</idno>
<date when="2013">2013</date>
<idno type="stanalyst">PASCAL 14-0082273 INIST</idno>
<idno type="RBID">Pascal:14-0082273</idno>
<idno type="wicri:Area/Main/Corpus">000112</idno>
<idno type="wicri:Area/Main/Repository">000563</idno>
</publicationStmt>
<seriesStmt><idno type="ISSN">0040-6090</idno>
<title level="j" type="abbreviated">Thin solid films</title>
<title level="j" type="main">Thin solid films</title>
</seriesStmt>
</fileDesc>
<profileDesc><textClass><keywords scheme="KwdEn" xml:lang="en"><term>Active layer</term>
<term>Electric field effect</term>
<term>Gallium oxide</term>
<term>Gates</term>
<term>Indium oxide</term>
<term>Interface</term>
<term>Logic gate</term>
<term>Scaling law</term>
<term>Thin film</term>
<term>Thin film transistor</term>
<term>Voltage threshold</term>
<term>Zinc oxide</term>
</keywords>
<keywords scheme="Pascal" xml:lang="fr"><term>Electrode commande</term>
<term>Transistor couche mince</term>
<term>Oxyde d'indium</term>
<term>Oxyde de gallium</term>
<term>Oxyde de zinc</term>
<term>Couche mince</term>
<term>Interface</term>
<term>Couche active</term>
<term>Porte logique</term>
<term>Effet champ électrique</term>
<term>Seuil tension</term>
<term>Loi échelle</term>
<term>InGaZnO</term>
<term>Al2O3</term>
<term>8530T</term>
<term>8530P</term>
</keywords>
</textClass>
</profileDesc>
</teiHeader>
<front><div type="abstract" xml:lang="en">Self-aligned top-gate amorphous indium-gallium-zinc oxide (a-IGZO) thin film transistors (TFTs) utilizing SiO<sub>2</sub>
/ Al<sub>2</sub>
O<sub>3</sub>
 stack thin films as gate dielectric are developed in this paper. Due to high quality of the high-k Al<sub>2</sub>
O<sub>3</sub>
 and good interface between active layer and gate dielectric, the resulting a-IGZO TFT exhibits good electrical performance including field-effect mobility of 9 cm<sup>2</sup>
/Vs, threshold voltage of 2.2 V, subthreshold swing of 0.2 V/decade, and on/off current ratio of 1 × 10<sup>7</sup>
. With scaling down of the channel length, good characteristics are also obtained with a small shift of the threshold voltage and no degradation of subthreshold swing.</div>
</front>
</TEI>
<inist><standard h6="B"><pA><fA01 i1="01" i2="1"><s0>0040-6090</s0>
</fA01>
<fA02 i1="01"><s0>THSFAP</s0>
</fA02>
<fA03 i2="1"><s0>Thin solid films</s0>
</fA03>
<fA05><s2>548</s2>
</fA05>
<fA08 i1="01" i2="1" l="ENG"><s1>Self-aligned top-gate InGaZnO thin film transistors using SiO<sub>2</sub>
/Al<sub>2</sub>
O<sub>3</sub>
 stack gate dielectric</s1>
</fA08>
<fA11 i1="01" i2="1"><s1>RONGSHENG CHEN</s1>
</fA11>
<fA11 i1="02" i2="1"><s1>WEI ZHOU</s1>
</fA11>
<fA11 i1="03" i2="1"><s1>MENG ZHANG</s1>
</fA11>
<fA11 i1="04" i2="1"><s1>MAN WONG</s1>
</fA11>
<fA11 i1="05" i2="1"><s1>HOI SING KWOK</s1>
</fA11>
<fA14 i1="01"><s1>Center for Display Research, Department of Electronic and Computer Engineering, Hong Kong University of Science and Technology, Clear Water Bay</s1>
<s2>Kowloon</s2>
<s3>HKG</s3>
<sZ>1 aut.</sZ>
<sZ>2 aut.</sZ>
<sZ>3 aut.</sZ>
<sZ>4 aut.</sZ>
<sZ>5 aut.</sZ>
</fA14>
<fA20><s1>572-575</s1>
</fA20>
<fA21><s1>2013</s1>
</fA21>
<fA23 i1="01"><s0>ENG</s0>
</fA23>
<fA43 i1="01"><s1>INIST</s1>
<s2>13597</s2>
<s5>354000505785000940</s5>
</fA43>
<fA44><s0>0000</s0>
<s1>© 2014 INIST-CNRS. All rights reserved.</s1>
</fA44>
<fA45><s0>13 ref.</s0>
</fA45>
<fA47 i1="01" i2="1"><s0>14-0082273</s0>
</fA47>
<fA60><s1>P</s1>
</fA60>
<fA61><s0>A</s0>
</fA61>
<fA64 i1="01" i2="1"><s0>Thin solid films</s0>
</fA64>
<fA66 i1="01"><s0>NLD</s0>
</fA66>
<fC01 i1="01" l="ENG"><s0>Self-aligned top-gate amorphous indium-gallium-zinc oxide (a-IGZO) thin film transistors (TFTs) utilizing SiO<sub>2</sub>
/ Al<sub>2</sub>
O<sub>3</sub>
 stack thin films as gate dielectric are developed in this paper. Due to high quality of the high-k Al<sub>2</sub>
O<sub>3</sub>
 and good interface between active layer and gate dielectric, the resulting a-IGZO TFT exhibits good electrical performance including field-effect mobility of 9 cm<sup>2</sup>
/Vs, threshold voltage of 2.2 V, subthreshold swing of 0.2 V/decade, and on/off current ratio of 1 × 10<sup>7</sup>
. With scaling down of the channel length, good characteristics are also obtained with a small shift of the threshold voltage and no degradation of subthreshold swing.</s0>
</fC01>
<fC02 i1="01" i2="X"><s0>001D03F04</s0>
</fC02>
<fC03 i1="01" i2="3" l="FRE"><s0>Electrode commande</s0>
<s5>01</s5>
</fC03>
<fC03 i1="01" i2="3" l="ENG"><s0>Gates</s0>
<s5>01</s5>
</fC03>
<fC03 i1="02" i2="X" l="FRE"><s0>Transistor couche mince</s0>
<s5>02</s5>
</fC03>
<fC03 i1="02" i2="X" l="ENG"><s0>Thin film transistor</s0>
<s5>02</s5>
</fC03>
<fC03 i1="02" i2="X" l="SPA"><s0>Transistor capa delgada</s0>
<s5>02</s5>
</fC03>
<fC03 i1="03" i2="X" l="FRE"><s0>Oxyde d'indium</s0>
<s5>03</s5>
</fC03>
<fC03 i1="03" i2="X" l="ENG"><s0>Indium oxide</s0>
<s5>03</s5>
</fC03>
<fC03 i1="03" i2="X" l="SPA"><s0>Indio óxido</s0>
<s5>03</s5>
</fC03>
<fC03 i1="04" i2="X" l="FRE"><s0>Oxyde de gallium</s0>
<s5>04</s5>
</fC03>
<fC03 i1="04" i2="X" l="ENG"><s0>Gallium oxide</s0>
<s5>04</s5>
</fC03>
<fC03 i1="04" i2="X" l="SPA"><s0>Galio óxido</s0>
<s5>04</s5>
</fC03>
<fC03 i1="05" i2="X" l="FRE"><s0>Oxyde de zinc</s0>
<s5>05</s5>
</fC03>
<fC03 i1="05" i2="X" l="ENG"><s0>Zinc oxide</s0>
<s5>05</s5>
</fC03>
<fC03 i1="05" i2="X" l="SPA"><s0>Zinc óxido</s0>
<s5>05</s5>
</fC03>
<fC03 i1="06" i2="X" l="FRE"><s0>Couche mince</s0>
<s5>06</s5>
</fC03>
<fC03 i1="06" i2="X" l="ENG"><s0>Thin film</s0>
<s5>06</s5>
</fC03>
<fC03 i1="06" i2="X" l="SPA"><s0>Capa fina</s0>
<s5>06</s5>
</fC03>
<fC03 i1="07" i2="X" l="FRE"><s0>Interface</s0>
<s5>07</s5>
</fC03>
<fC03 i1="07" i2="X" l="ENG"><s0>Interface</s0>
<s5>07</s5>
</fC03>
<fC03 i1="07" i2="X" l="SPA"><s0>Interfase</s0>
<s5>07</s5>
</fC03>
<fC03 i1="08" i2="X" l="FRE"><s0>Couche active</s0>
<s5>08</s5>
</fC03>
<fC03 i1="08" i2="X" l="ENG"><s0>Active layer</s0>
<s5>08</s5>
</fC03>
<fC03 i1="08" i2="X" l="SPA"><s0>Capa activa</s0>
<s5>08</s5>
</fC03>
<fC03 i1="09" i2="X" l="FRE"><s0>Porte logique</s0>
<s5>09</s5>
</fC03>
<fC03 i1="09" i2="X" l="ENG"><s0>Logic gate</s0>
<s5>09</s5>
</fC03>
<fC03 i1="09" i2="X" l="SPA"><s0>Puerta lógica</s0>
<s5>09</s5>
</fC03>
<fC03 i1="10" i2="X" l="FRE"><s0>Effet champ électrique</s0>
<s5>10</s5>
</fC03>
<fC03 i1="10" i2="X" l="ENG"><s0>Electric field effect</s0>
<s5>10</s5>
</fC03>
<fC03 i1="10" i2="X" l="SPA"><s0>Efecto campo eléctrico</s0>
<s5>10</s5>
</fC03>
<fC03 i1="11" i2="X" l="FRE"><s0>Seuil tension</s0>
<s5>11</s5>
</fC03>
<fC03 i1="11" i2="X" l="ENG"><s0>Voltage threshold</s0>
<s5>11</s5>
</fC03>
<fC03 i1="11" i2="X" l="SPA"><s0>Umbral tensión</s0>
<s5>11</s5>
</fC03>
<fC03 i1="12" i2="X" l="FRE"><s0>Loi échelle</s0>
<s5>12</s5>
</fC03>
<fC03 i1="12" i2="X" l="ENG"><s0>Scaling law</s0>
<s5>12</s5>
</fC03>
<fC03 i1="12" i2="X" l="SPA"><s0>Ley escala</s0>
<s5>12</s5>
</fC03>
<fC03 i1="13" i2="X" l="FRE"><s0>InGaZnO</s0>
<s4>INC</s4>
<s5>46</s5>
</fC03>
<fC03 i1="14" i2="X" l="FRE"><s0>Al2O3</s0>
<s4>INC</s4>
<s5>47</s5>
</fC03>
<fC03 i1="15" i2="X" l="FRE"><s0>8530T</s0>
<s4>INC</s4>
<s5>71</s5>
</fC03>
<fC03 i1="16" i2="X" l="FRE"><s0>8530P</s0>
<s4>INC</s4>
<s5>72</s5>
</fC03>
<fN21><s1>111</s1>
</fN21>
<fN44 i1="01"><s1>OTO</s1>
</fN44>
<fN82><s1>OTO</s1>
</fN82>
</pA>
</standard>
</inist>
</record>

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Self-aligned top-gate InGaZnO thin film transistors using SiO2/Al2O3 stack gate dielectric

Self-aligned top-gate InGaZnO thin film transistors using SiO2/Al2O3 stack gate dielectric

Descripteurs français

English descriptors

Abstract

Links toward previous steps (curation, corpus...)

Links to Exploration step

Le document en format XML

Pour manipuler ce document sous Unix (Dilib)

Pour mettre un lien sur cette page dans le réseau Wicri